1. Field of the Invention
The present invention relates to analog-to-digital conversion circuits. More particularly, the present invention relates to flash analog-to-digital conversion circuits.
2. Background Art
The flash architecture is a widely used form of analog-to-digital converter (ADC). Flash ADCs can be used in a standalone fashion, which is often utilized in high-speed applications. More often flash ADCs are used as part of other ADCs, such as pipeline ADCs, folding and interpolating ADCs, subranging ADCs, and multi-bit delta sigma modulators.
A conventional standalone flash ADC is shown in circuit 100 of FIG. 1. Circuit 100 includes two voltage sources, three resistors, three voltage comparators, and an encoder. In operation, reference source 102 can provide a fixed reference voltage to circuit 100. The output of reference source 102 is coupled to the first end of resistor 110, the second end of resistor 110 is coupled to the first end of resistor 112, the second end of resistor 112 is coupled to the first end of resistor 114, and the second end of resistor 114 is coupled to ground 106. In this configuration, resistors 110 through 114 form a voltage divider, and a fixed voltage at a level between the reference source 102 voltage and the ground 106 voltage can exist between the second end and first end of each resistor pair. The voltage between resistors 110 and 112 is lower than the reference source 102 voltage, and the voltage between resistors 112 and 114 is lower than the voltage between resistors 110 and 112.
First voltage comparator 120, second voltage comparator 130, and third voltage comparator 140 each has a reference input, a signal input, and an output. The reference input and the signal input of each voltage comparator can receive analog voltage signals, which in operation are then compared by voltage comparators 120, 130 and 140. If the reference input voltage is higher than the signal input voltage, the voltage comparator output will be set to logic low. Conversely, if the reference input voltage is lower than the signal input voltage, the voltage comparator output will be set to logic high.
The reference input of first voltage comparator 120 is coupled to reference source 102 and to the first end of resistor 110, the reference input of second voltage comparator 130 is coupled to the second end of resistor 110 and the first end of resistor 112, and the reference input of third voltage comparator 140 is coupled to the second end of resistor 112 and the first end of resistor 114. In this configuration, the reference inputs of voltage comparators 120, 130 and 140 each receive a different voltage from the voltage divider. The output of signal source 104 is coupled to the signal input of first voltage comparator 120, to the signal input of second voltage comparator 130, and to the signal input of third voltage comparator 140. In this configuration, the signal inputs of voltage comparators 120, 130 and 140 each receive the same voltage from the output of signal source 104.
In operation, signal source 104 can provide an analog voltage to circuit 100 for conversion to a digital (i.e. logic level) voltage. The voltage output by signal source 104 may be higher or lower than the voltage received by the reference inputs of voltage comparators 120 through 140. For instance, reference input of first voltage comparator 120 receives the reference source 102 voltage. If the reference source 102 voltage is higher than the signal source 104 voltage received by the signal input of first voltage comparator 120, the first voltage comparator 120 output will be set to logic low. Second voltage comparator 130 and third voltage comparator 140 will perform similar comparisons.
Because of the structure of the voltage divider assembled from resistors 110 through 114, the voltage received by the reference input of second voltage comparator 130 is lower than the voltage received by the reference input of first voltage comparator 120, and the voltage received by the reference input of third voltage comparator 140 is lower than the voltage received by the reference input of second voltage comparator 130. Consequently, if the signal source 104 voltage is high enough to make first voltage comparator 120 output a logic high, voltage comparators 130 and 140 also output logic high. Similarly, if the signal source 104 voltage is not high enough to make first voltage comparator 120 output a logic high, but is high enough to make second voltage comparator 130 output a logic high, then the third voltage comparator 140 output will also be logic high.
The result of the analog-to-digital conversion is represented by the cardinality of voltage comparator outputs that are set logic high. For instance, if in operation the signal source 104 voltage exceeds the reference source 102 voltage, then each voltage comparator output will be set logic high, because the signal input of each voltage comparator receives a voltage that exceeds the voltage received by the reference input of each voltage comparator. Thus, in circuit 100, the cardinality of voltage comparator outputs that are set logic high is three (3). However, if the signal source 104 voltage is reduced below the reference source 102 voltage, but remains above the voltage between the second end of resistor 110 and the first end of resistor 112, then the first voltage comparator 120 output will be set logic low, while the remaining voltage comparator 130 and 140 outputs will continue to be logic high. In this fashion, the cardinality of voltage comparator outputs that are set logic high, and thus the result of the analog-to-digital conversion, declines from 3 to 2 as the signal source 104 voltage declines. In circuit 100, this cardinal output (i.e., a base-1 output, or “thermometer code”) can be converted by encoder 150 to, for instance, a binary number (i.e., a base-2 output).
One clear disadvantage of flash ADC circuit 100 follows as a consequence of its base-1 voltage comparator output, which is that to be able to resolve N binary digits, flash ADC circuit 100 must be assembled from 2^N−1 voltage comparators. For example, circuit 100, which can resolve between 2 binary digits on the output of encoder 150, is assembled from three (3) voltage comparators. As the binary resolution of flash ADC circuit 100 increases, the exponential increase in the required number of voltage comparators becomes prohibitively expensive. For instance, a flash ADC that can resolve between eight (8) binary digits would require 255 voltage comparators. This exponential growth in the number of voltage comparators translates directly to exponential growth in circuit die size, to exponential growth in circuit power consumption, and to increasing difficulty in driving the reference source and signal source because of increased capacitive loading.
A number of conventional solutions have been designed that attempt to cope with the problems of increasing circuit size, power, and capacitive loading. One such solution, for example, is seen in circuit 200 of FIG. 2. In circuit 200, reference source 202, signal source 204, ground 206, and the voltage divider assembled from resistors 210 through 214 are functionally similar to their counterparts in circuit 100, as are voltage comparators 220 through 240 and encoder 250. However, instead of directly coupling to voltage comparators 220 through 240, the voltage divider is coupled to an intermediary interpolator stage that can be assembled from, for example, an array of amplifiers 260 through 270 connected to an interpolating network of resistors 280 through 296. The interpolator stage reduces the capacitive load on reference source 202 and signal source 204, because the three amplifiers 260 through 270 are easier to drive than the six subsequent voltage comparators. While circuit 200 is easier to drive than a pure flash ADC, and allows for the use of smaller voltage comparators without sacrificing accuracy, the interpolator stage of circuit 200 also significantly reduces overall conversion speed and bandwidth.
Another conventional solution, namely, the subranging ADC, reduces capacitive loading and circuit size at the cost of significantly increased conversion time. Subranging ADCs typically contain two flash ADCs, and perform analog-to-digital conversion in two stages. The first, coarse stage determines a voltage subrange where the signal input voltage exists, and then the second, fine stage determines where in the subrange the signal input voltage exists. Thus, in a subranging ADC with N binary output bits, the first stage can calculate the most-significant first half of the bits, and the second stage can calculate the least-significant second half of the bits. Because the conversion is done in two stages, the number of voltage comparators used can be reduced from 2^N−1 (as is the case in a flash ADC, for instance circuit 100) to 2*(2^(N/2)−1). For example, a pure flash ADC designed to calculate an 8-bit binary output would require 255 voltage comparators, whereas a subranging ADC designed to calculate the same result would require only 30 voltage comparators. While the attendant reduction in circuit size is laudable, the time required to split the conversion process into two steps makes subranging ADCs completely unsuitable for high-speed applications.
Therefore, there is an intense need in the art for analog-to-digital conversion circuits that can provide speed and accuracy, and further reduce the circuit size, power and cost.